MOSFET Subthreshold Swing & DIBL Calculator

Comprehensive MOSFET Subthreshold Physics & DIBL Engineering Guide

In modern complementary metal-oxide-semiconductor (CMOS) integrated circuits containing tens of billions of transistors, power dissipation has surpassed frequency scaling as the supreme performance limiter. As channel lengths shrank below 100 nanometers toward advanced 3nm and 2nm nodes, short-channel electrostatic effects—specifically **Subthreshold Swing ($SS$)** degradation and **Drain-Induced Barrier Lowering (DIBL)**—became the dominant physical mechanisms driving exponential increases in standby leakage power.

1. Fundamental Subthreshold Conduction Physics

When the gate-to-source voltage $V_{gs}$ is below the threshold voltage $V_{th}$ ($V_{gs} < V_{th}$), the silicon surface is not strongly inverted. However, the transistor is not completely off. The channel operates in weak inversion, where minority carriers (electrons in an n-MOSFET) do not drift under electric fields but instead diffuse across the source-channel potential energy barrier like in a forward-biased p-n junction.

The electron concentration at the barrier peak follows Boltzmann statistics: $n_s propto expleft(frac{q psi_s}{k_B T}right)$, where $psi_s$ is the surface potential. The subthreshold drain current is:

where $V_t = frac{k_B T}{q}$ is the thermal voltage ($25.86text{ mV}$ at $300text{ K}$) and $m$ is the capacitive body ideality factor.

2. The Thermodynamic 60 mV/decade Subthreshold Swing Limit

The **Subthreshold Swing ($SS$)** quantifies the gate voltage required to modulate drain current by one order of magnitude (a factor of 10):

The capacitive voltage divider between the gate oxide capacitance $C_{ox}$, silicon depletion capacitance $C_{dep}$, and interface trap capacitance $C_{it} = q^2 D_{it}$ dictates the body factor $m$:

In an ideal transistor with zero depletion capacitance ($C_{dep} = 0$, as approached by ultra-thin body FDSOI or Gate-All-Around nanosheets) and zero interface traps ($D_{it} = 0$), $m = 1.0$. This yields the **fundamental Boltzmann thermal limit**:

Because this limit is dictated by Maxwell-Boltzmann carrier energy tails, conventional MOSFETs cannot switch faster than $approx 60text{ mV/decade}$ at room temperature, necessitating novel steep-slope devices (Negative Capacitance FETs, Tunnel FETs) for sub-0.5V operation.

3. Drain-Induced Barrier Lowering (DIBL) Mechanism

In long-channel MOSFETs, the potential barrier controlling carrier flow from source into the channel is modulated exclusively by the gate voltage. However, when the channel length $L_g$ shrinks below $approx 50text{ nm}$, the depletion region of the reverse-biased drain junction extends across the entire channel length, electrostatically coupling with the source barrier.

Applying a high drain voltage ($V_{ds} = V_{dd}$) pulls down the conduction band edge barrier height by $Delta phi_B approx frac{q cdot text{DIBL} cdot V_{ds}}{1000}$. This causes the effective threshold voltage to roll off:

DIBL severely accelerates OFF-state leakage current and degrades output resistance ($r_o = 1/g_{ds}$), reducing intrinsic analog amplifier voltage gain ($A_v = g_m r_o$).

4. OFF-State Leakage Current ($I_{off}$) and Static Chip Power

At $V_{gs} = 0text{ V}$, the standby leakage current per unit transistor width is:

where $I_{th}$ is defined at $V_{gs} = V_{th}$ (standardized as $100text{ nA/µm}$). Notice the extreme sensitivity: a mere $60text{ mV}$ drop in threshold voltage or a $10text{ mV/dec}$ degradation in subthreshold swing increases static leakage current by a full order of magnitude ($10times$).

The total static power dissipated by an un-clocked logic block with $N_{trans}$ transistors and average gate width $W$ is:

5. Technological Evolution: Planar to FinFET to Gate-All-Around (GAA)

6. Step-by-Step Worked Nanoscale Transistor Sizing Example

Analyze a high-performance 7nm FinFET logic transistor operating at $T = 300text{ K}$:

• Equivalent Oxide Thickness $text{EOT} = 1.0text{ nm} = 1.0 times 10^{-7}text{ cm}$
• Substrate channel doping $N_A = 2.0 times 10^{17}text{ cm}^{-3}$
• Nominal threshold voltage $V_{th0} = 0.30text{ V}$ at $V_{ds} = 0.05text{ V}$
• Measured DIBL $= 45text{ mV/V}$
• Operating supply voltage $V_{dd} = 0.75text{ V}$
• Normalized threshold current $I_{th} = 100text{ nA/µm}$
• Interface trap state density $D_{it} = 1.0 times 10^{11}text{ cm}^{-2}text{eV}^{-1}$

Step 1: Calculate Gate Oxide Capacitance ($C_{ox}$)

Step 2: Calculate Depletion and Interface Trap Capacitance

Fermi potential $phi_F = frac{k_B T}{q} lnleft(frac{N_A}{n_i}right) approx 0.02586 lnleft(frac{2 times 10^{17}}{1.0 times 10^{10}}right) approx 0.435text{ V}$. Maximum depletion width:

Step 3: Calculate Subthreshold Swing ($SS$)

Step 4: Compute High-Drain Threshold Shift and Leakage Current

The FinFET exhibits near-ideal electrostatics ($62.2text{ mV/dec}$), maintaining an ultra-low leakage current of under $5text{ pA}$ per micron of gate width.

7. Steep-Slope Innovations: Negative Capacitance FETs (NC-FETs)

To break the fundamental thermodynamic Boltzmann limit of $60text{ mV/decade}$ at room temperature, researchers exploit internal voltage amplification using ferroelectric materials (such as doped hafnium zirconium oxide, $Hf_{1-x}Zr_xO_2$). Integrating a thin ferroelectric dielectric in the gate stack produces a stabilized **negative capacitance** state ($C_{fe} < 0$) in the Landau-Khalatnikov polarization loop:

When internal voltage amplification exceeds unity ($A_v > 1$), the body factor drops below one ($m < 1$), achieving sub-thermionic subthreshold swings ($SS < 50text{ mV/dec}$) without requiring cryogenic cooling, potentially enabling sub-0.4V logic operation.

8. Competing OFF-State Leakage Mechanisms: GIDL & BTBT

At negative or zero gate biases ($V_{gs} le 0$), drain leakage is not restricted to subthreshold diffusion alone:

• Gate-Induced Drain Leakage (GIDL): The intense transverse electric field across the gate-to-drain overlap region ($E_{ox} > 5text{ MV/cm}$) creates an aggressive deep-depletion layer in the heavily doped n+ drain. Band-to-band tunneling occurs, sweeping generated electrons into the drain and holes into the substrate.
• Source-to-Drain Direct Quantum Tunneling: In sub-5nm physical gate lengths ($L_g < 5text{ nm}$), the channel barrier width is so narrow that electrons tunnel directly from source to drain quantum mechanically through the barrier, bypassing thermal emission and creating a hard floor on achievable $I_{off}$.