1. Theoretical Foundation: Flyback Coupled Inductors
The isolated flyback switched-mode power supply (SMPS) is the ubiquitous topology of choice for low-to-medium power conversion applications (typically from 1 Watt to 150 Watts), spanning mobile USB-C chargers, offline auxiliary supplies in industrial drives, automotive battery management front-ends, and LED lighting drivers. Despite its widespread moniker of "flyback transformer," the core magnetic component behaves fundamentally as a gapped multi-winding energy storage inductor rather than an instantaneous voltage-ratio transformer.
During the primary transistor conduction phase ($t_{ ext{on}} = D cdot T_{ ext{sw}}$):
- The primary MOSFET turns ON, applying the rectified DC input voltage ($V_{ ext{in}}$) across the primary winding ($N_p$).
- Current ramps linearly upward through the primary winding at a rate governed by Faraday's Law: $$ rac{di_{ ext{pri}}}{dt} = rac{V_{ ext{in}}}{L_p}$$
- The secondary winding diode is reverse-biased due to the opposite polarity winding dots. Zero energy is transferred to the load during this phase; instead, energy is accumulated in the magnetic field localized within the core air gap: $$E_{ ext{stored}} = rac{1}{2} L_p I_{ ext{pk,pri}}^2$$
During the secondary flyback conduction phase ($t_{ ext{off}} = (1 - D) cdot T_{ ext{sw}}$):
- The primary MOSFET abruptly turns OFF. By Lenz's law, the magnetic field begins to collapse, reversing the polarities across all windings.
- The secondary diode becomes forward-biased, clamping the secondary winding voltage to $V_{ ext{out}} + V_F$.
- The stored magnetic energy discharges into the output capacitor and load, with secondary current ramping down to zero: $$ rac{di_{ ext{sec}}}{dt} = - rac{V_{ ext{out}} + V_F}{L_s}$$
2. DCM vs CCM Operating Modes: Engineering Tradeoffs
The flyback converter can operate in two distinct conduction regimes depending on whether the core completely demagnetizes before the next switching period:
| Design Characteristic | Discontinuous Conduction Mode (DCM) | Continuous Conduction Mode (CCM) |
|---|---|---|
| Core Demagnetization | Complete ($I_{ ext{sec}}$ reaches zero; includes dead time / idle ringing). | Incomplete ($I_{ ext{sec}}$ remains above zero when MOSFET turns back ON). |
| Ripple Factor ($K_{ ext{RP}}$) | $K_{ ext{RP}} ge 1.0$ ($K_{ ext{RP}} = Delta I / I_{ ext{pk}} = 1.0$) | $K_{ ext{RP}} < 1.0$ (typically $0.4 le K_{ ext{RP}} le 0.6$) |
| Primary Inductance ($L_p$) | Smaller inductance required; smaller magnetic core volume. | 2× to 4× larger inductance required; larger core size. |
| Peak & RMS Currents | High peak current ($I_{ ext{pk}} = 2 P_{ ext{in}} / (V_{ ext{in}} D)$); higher copper and capacitor ESR losses. | Lower peak current ($I_{ ext{pk}} approx P_{ ext{in}} / (V_{ ext{in}} D) + Delta I / 2$); lower RMS current stress. |
| Secondary Diode Recovery | Zero reverse recovery loss (diode naturally commutates at zero current). | Severe reverse recovery losses; requires ultra-fast or silicon carbide (SiC) diodes. |
| Control Loop Dynamics | Single low-frequency pole; simple Type II feedback compensation; no RHP zero. | Contains a Right-Half-Plane (RHP) Zero that limits loop bandwidth and gain margin. |
| Preferred Applications | Sub-50W AC-DC adapters, low output voltage / high current converters, wide-input supplies. | 50W to 150W converters, high continuous power supplies where RMS losses dominate. |
3. Complete Mathematical Design Workflow
3.1 Reflected Voltage & Duty Cycle
When the primary switch opens, the secondary voltage $(V_{ ext{out}} + V_F)$ is transformed back across the primary winding by the turns ratio $n = N_p / N_s$. This reflected voltage is termed $V_{or}$:
$$V_{or} = n cdot (V_{ ext{out}} + V_F)$$The maximum duty cycle $D_{ ext{max}}$ occurs at the minimum input voltage $V_{ ext{in,min}}$:
$$D_{ ext{max}} = rac{V_{or}}{V_{or} + V_{ ext{in,min}}}$$ $$V_{or} = V_{ ext{in,min}} cdot rac{D_{ ext{max}}}{1 - D_{ ext{max}}}$$3.2 Primary Inductance Derivation
Assuming a converter efficiency $eta$ (typically $0.80$ to $0.88$), input power is $P_{ ext{in}} = P_{ ext{out}} / eta$. In DCM, the full energy per cycle is discharged:
$$P_{ ext{in}} = rac{1}{2} L_p I_{ ext{pk,pri}}^2 f_{ ext{sw}}$$Combining this with $I_{ ext{pk,pri}} = rac{V_{ ext{in,min}} D_{ ext{max}}}{L_p f_{ ext{sw}}}$ yields the primary inductance equation:
$$L_p = rac{eta cdot V_{ ext{in,min}}^2 cdot D_{ ext{max}}^2}{2 cdot P_{ ext{out}} cdot f_{ ext{sw}}}$$3.3 Core Air Gap & Minimum Primary Turns
To avoid magnetic core saturation under maximum peak current, the peak flux density must not exceed the design flux density $B_{ ext{max}}$ (typically $0.22 ext{ to }0.25 ext{ Tesla}$ for MnZn ferrites):
$$N_p = rac{L_p cdot I_{ ext{pk,pri}}}{B_{ ext{max}} cdot A_e cdot 10^{-6}}$$where $A_e$ is expressed in $ ext{mm}^2$. The secondary turns follow directly from the turns ratio:
$$n = rac{V_{or}}{V_{ ext{out}} + V_F} implies N_s = leftlceil rac{N_p}{n} ight ceil$$The physical center air gap length $l_g$ (in millimeters) is computed via Ampere's circuital law:
$$l_g = rac{mu_0 cdot N_p^2 cdot A_e cdot 10^{-6}}{L_p} imes 10^3 = rac{4pi imes 10^{-4} cdot N_p^2 cdot A_e}{L_p}$$4. Semiconductor Stress & Snubber Design
The primary power MOSFET encounters severe electrical stress at turn-off due to the superposition of three voltage components:
$$V_{ ext{DS,max}} = V_{ ext{in,max}} + V_{or} + V_{ ext{spike}}$$where $V_{ ext{spike}}$ is the inductive transient caused by primary leakage inductance ($L_{ ext{lk}}$), typically 1% to 3% of $L_p$. Without an effective snubber, $V_{ ext{DS}}$ will violently avalanche and destroy the MOSFET. An RCD (Resistor-Capacitor-Diode) clamp circuit is placed across the primary winding to absorb this leakage energy:
$$P_{ ext{snubber}} = rac{1}{2} L_{ ext{lk}} I_{ ext{pk,pri}}^2 f_{ ext{sw}} cdot rac{V_{ ext{clamp}}}{V_{ ext{clamp}} - V_{or}}$$Similarly, the secondary rectifier diode experiences peak reverse voltage when the primary switch conducts:
$$V_{ ext{diode,PIV}} = V_{ ext{out}} + rac{V_{ ext{in,max}}}{n}$$5. High-Frequency Winding & Proximity Losses
At switching frequencies above 50 kHz, skin effect and proximity effect severely elevate the AC resistance of the copper windings. The electromagnetic skin depth $delta$ in copper at temperature $T = 70^circ ext{C}$ is:
$$delta = rac{66.1}{sqrt{f_{ ext{sw}}}} quad ( ext{in mm})$$At $f_{ ext{sw}} = 65 ext{ kHz}$, the skin depth is approximately $0.26 ext{ mm}$. Wire conductors with diameter exceeding $2delta = 0.52 ext{ mm}$ (approx. AWG 24) suffer severe skin effect degradation. To minimize AC copper losses, engineers must utilize:
- Multifilar Windings: Paralleling multiple smaller-gauge insulated magnetic wires (e.g. 3× AWG 28 instead of 1× AWG 20).
- Litz Wire: Woven bunches of individually insulated fine strands for frequencies above 100 kHz.
- Sandwich Winding Construction: Splitting the primary winding into two halves ($P_1$ on the inside, secondary winding $S$ in the middle, and $P_2$ on the outside). This interleaved construction reduces leakage inductance by a factor of 3 to 4, drastically cutting snubber dissipation.
6. Worked Design Example: Universal AC 12V / 2.5A Flyback
Design Specifications: $V_{ ext{in}} = 85 ext{–}265 ext{ VAC}$ (giving $V_{ ext{in,min}} = 100 ext{V DC}$, $V_{ ext{in,max}} = 375 ext{V DC}$), $V_{ ext{out}} = 12 ext{V DC}$, $I_{ ext{out}} = 2.5 ext{A}$ ($P_{ ext{out}} = 30 ext{W}$), $f_{ ext{sw}} = 65 ext{ kHz}$, $eta = 85%$, Target $D_{ ext{max}} = 0.45$. Ferrite Core: EE25 ($A_e = 51.5 ext{ mm}^2$).
Step 1: Reflected Voltage & Primary Inductance
$$V_{or} = 100 ext{ V} imes rac{0.45}{1 - 0.45} = 81.8 ext{ V}$$ $$L_p = rac{0.85 imes (100)^2 imes (0.45)^2}{2 imes 30 imes 65,000} = rac{1,721.25}{3,900,000} = 441 imes 10^{-6} ext{ H} approx 440 ext{–}580 ext{ }mu ext{H}$$Step 2: Peak Primary Current
$$I_{ ext{pk,pri}} = rac{100 ext{ V} imes 0.45}{582 imes 10^{-6} ext{ H} imes 65,000 ext{ Hz}} = 1.36 ext{ Amps}$$Step 3: Primary & Secondary Turns
With $B_{ ext{max}} = 0.24 ext{ T}$ and $A_e = 51.5 ext{ mm}^2$:
$$N_p = rac{582 imes 10^{-6} imes 1.36}{0.24 imes 51.5 imes 10^{-6}} = rac{7.915 imes 10^{-4}}{1.236 imes 10^{-5}} = 64 ext{ turns}$$ $$n = rac{V_{or}}{V_{ ext{out}} + V_F} = rac{81.8}{12 + 0.7} = 6.44 implies N_s = rac{64}{6.44} = 9.94 approx 10 ext{ turns}$$Step 4: Air Gap Calculation
$$l_g = rac{4pi imes 10^{-7} imes (64)^2 imes 51.5 imes 10^{-6}}{582 imes 10^{-6}} imes 10^3 = 0.45 ext{ mm}$$A center-leg grind gap of $0.45 ext{ mm}$ (or spacer tape of $0.225 ext{ mm}$ on both outer legs) achieves the exact required inductance without saturation.