Phase-Locked Loop (PLL) Loop Filter Bandwidth Calculator

Comprehensive Phase-Locked Loop (PLL) Loop Filter Theory Guide

The Charge-Pump Phase-Locked Loop (CP-PLL) is an indispensable feedback control subsystem in modern electronics, providing low-jitter frequency synthesis, local oscillator generation for radio transceivers, clock multiplication for microprocessors, and clock-and-data recovery (CDR) in high-speed serial links. Designing the passive loop filter involves balancing contradictory requirements: broad loop bandwidth accelerates transient frequency locking and suppresses slow VCO phase noise, but amplifies reference spurs and degrades high-frequency noise filtering.

1. Mathematical Architecture of the Charge-Pump PLL

A classical Type-2 integer-N PLL synthesizer incorporates five fundamental blocks connected in a closed negative feedback loop:

• Phase-Frequency Detector (PFD): Compares the reference clock ($f_{ref}$) and feedback divider clock ($f_{fb}$), producing tri-state Up and Down pulses proportional to the phase error $theta_e = theta_{ref} - theta_{fb}$.
• Charge Pump (CP): Converts digital Up/Down pulses into bidirectional current pulses of magnitude $pm I_{cp}$. The average phase detector transfer gain is:
  $$K_{pd} = frac{I_{cp}}{2pi}quad [text{A/rad}]$$
• Passive Loop Filter ($Z_f(s)$): Integrates charge-pump current pulses into an analog control voltage $V_{tune}(s) = I_{cp}(s) cdot Z_f(s)$.
• Voltage-Controlled Oscillator (VCO): Produces an output RF signal whose angular frequency varies linearly with control voltage: $omega_{out} = omega_0 + K_{vco} V_{tune}$. Because phase is the time integral of frequency ($theta(t) = int omega(t) dt$), the VCO acts as an ideal integrator in phase space:
  $$H_{vco}(s) = frac{K_{vco}}{s}quad [text{rad}/(text{V}cdottext{s})]$$
• Feedback Frequency Divider ($N$): Scales output frequency down to the comparison rate: $f_{ref} = f_{out} / N$. In phase space, it scales phase by $1/N$:
  $$H_{div}(s) = frac{1}{N}$$

2. Passive 2nd-Order and 3rd-Order Filter Transfer Functions

A purely capacitive filter ($1/sC$) yields an open-loop system with two poles at $s = 0$ (one from the filter, one from the VCO), resulting in a phase lag of $-180^circ$ and complete instability. To establish stability, a zero must be inserted.

A. 2nd-Order Passive Loop Filter Impedance

The standard 2nd-order topology connects a series network of $R_2$ and $C_2$ in parallel with a smaller capacitor $C_1$:

where the time constants are:

• Zero Time Constant: $tau_z = R_2 C_2$ introduces a phase lead zero at $omega_z = 1 / tau_z$.
• High-Frequency Pole Time Constant: $tau_p = R_2 frac{C_1 C_2}{C_1 + C_2} approx R_2 C_1$ (since $C_1 ll C_2$) places a pole at $omega_p = 1 / tau_p$ to suppress discrete charge-pump switching ripple.
• Total Capacitance: $C_{tot} = C_1 + C_2$.

B. Open-Loop Gain and Phase Margin Formulation

The open-loop transfer function of the PLL is:

The phase of $G_{ol}(jomega)$ is given by:

To maximize phase margin at the crossover frequency $omega_c = 2pi f_c$, $omega_c$ must be placed at the geometric mean of the zero and pole:

Using the trigonometric identity $tan(phi_m) = frac{omega_c tau_z - omega_c tau_p}{1 + omega_c^2 tau_z tau_p}$, we derive:

3. Component Sizing Synthesis Equations

Equating open-loop magnitude $|G_{ol}(jomega_c)| = 1$ at crossover yields:

C. Optional 3rd-Order Filter Pole ($R_3, C_3$)

To further attenuate reference spurs at $f_{ref}$ by an additional 10 to 20 dB, an RC low-pass pole ($omega_{p3} = 1 / (R_3 C_3)$) is appended before the VCO tuning port. To avoid degrading loop phase margin by more than $2^circ$ to $5^circ$, the pole is typically positioned at:

4. Stability, Gardner Limit, and Lock Time Estimation

Because the PFD operates as a sampled-data discrete phase detector at sampling rate $f_{ref}$, continuous-time Laplace approximation holds only when the loop bandwidth satisfies the **Gardner stability criterion**:

Exceeding $f_{ref}/10$ causes high-frequency sampled-data phase lag, leading to parametric instability and chaotic cycle slipping.

Transient Lock Time ($T_{lock}$)

When switching across a frequency step $Delta f$, the synthesizer experiences two operational phases:

1. Frequency Pull-In (Non-linear cycle slipping): If the frequency step exceeds the pull-in range, the PFD slips cycles. The pull-in time scales inversely with loop bandwidth squared.
2. Phase Acquisition (Linear settling): Once within the lock range, the frequency settles exponentially according to natural frequency $omega_n = sqrt{frac{I_{cp} K_{vco}}{2pi N C_2}}$ and damping factor $zeta = frac{R_2 C_2 omega_n}{2}$:
   $$T_{settle} approx frac{-ln(text{tolerance})}{zeta omega_n} approx frac{4 dots 5}{zeta omega_n} approx frac{4}{omega_c}$$

5. Step-by-Step Worked Synthesizer Design Example

Synthesize a local oscillator for an IEEE 802.15.4 / Bluetooth LE transceiver:

• Carrier Frequency $f_{out} = 2440text{ MHz}$
• PFD Reference Frequency $f_{ref} = 20text{ MHz}$
• Divider Ratio $N = 2440 / 20 = 122$
• VCO Tuning Sensitivity $K_{vco} = 40text{ MHz/V} = 40 times 10^6 times 2pitext{ rad}/(text{V}cdottext{s}) approx 2.513 times 10^8text{ rad}/(text{V}cdottext{s})$
• Charge Pump Current $I_{cp} = 2.0text{ mA} = 2.0 times 10^{-3}text{ A}$
• Target Bandwidth $f_c = 100text{ kHz} implies omega_c = 2pi times 10^5 approx 6.283 times 10^5text{ rad/s}$ ($f_c / f_{ref} = 0.005 ll 0.1$, unconditionally stable)
• Target Phase Margin $phi_m = 50^circ$

Step 1: Compute Zero and Pole Time Constants

Step 2: Calculate Loop Filter Capacitors and Resistors

Step 3: Sizing 3rd-Order Attenuation Filter

Step 4: Lock Time Verification

The frequency synthesizes in under $7text{ µs}$ with phase margin exceeding $50^circ$, ensuring fast channel hopping across the 2.4 GHz ISM band.

6. Phase Margin vs Synthesizer Performance Trade-Off Matrix